1. Field of the Invention
The present invention relates generally to multichip modules and more particularly to the manner in which electrical connections are made to the module or between chips in the module.
2. Description of the Related Art
As electronic products move to smaller size and higher density and performance, semiconductors have correspondingly become smaller with their components and connections becoming denser. This in turn has lead to the development of multichip package (MCPs) in which a plurality of semiconductor chips are stacked on a substrate such as a printed circuit board. This creates a high density, high performance package that is nonetheless small in size.
As density increases and size decreases, however, problems may develop with multichip modules. For example, in FIG. 1, an MCP includes a first semiconductor chip 10 mounted on a substrate 12. A second semiconductor chip 14 is mounted on semiconductor chip 10 thereby forming an MCP comprising semiconductor chips 10, 14. Chip 10, which is larger than chip 14, includes terminals such as terminals 16, 18. Chip 14 also includes terminals, like terminals 20, 22. As can be seen, the terminals on chip 14 are spaced much more closely together than those on chip 10. The terminals on both chips are electrically connected to conductive pads, like pads 24, 26, formed on substrate 12 via wire bonds, such as wire bonds 28, 30.
The terminals on chip 14, like terminals 20, 22, are further away and higher from substrate 12 than the terminals, like terminals 16, 18, on chip 10. As a result, the wire bonds connecting the terminals on chip 14 to substrate 12 are longer and form a greater angle relative to the substrate than the wire bonds that connect the terminals on chip 10 to the substrate pads. And the terminals on chip 14 are much closer together. All these factors may combine to produce wire sweeping, in which the wire bonds connecting the terminals on chip 14 to the substrate pads electrically short against one another. Also, the longer each wire bond, the more likely the wire will be broken during manufacturing, e.g., when the wires are encapsulated.
In addition to these problems, when the terminals are close together as on chip 14, there is a limit to how many adjacent terminals can be wire bonded to the substrate. As seen in FIG. 1, there is a gap indicated generally at 31 that must be included because the density and length of the bonds limit the number of adjacent wire bond connections.
It would be desirable to provide wire bonds or other electrical connections on the upper chip of an MCP that are shorter and have a smaller bonding angle relative to the substrate. One approach uses a redistribution network, but it cannot be employed in some types of chips because the chip design must include certain electrical characteristics, and this complicates chip design.
Another approach uses an interposer, but this increases fabrication cost and does not completely resolve the problems associated with long wires, terminals at a high elevation relative to the substrate, and large bonding angles.